1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for using scatterometry to measure overlay errors.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today""s manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Among the factors that affect semiconductor device manufacturing are wafer-to-wafer variations that are caused by manufacturing problems that include start-up effects of manufacturing machine tools, memory effects of manufacturing chambers, and first-wafer effects. One of the process steps that is adversely affected by such factors is the photolithography overlay process. Overlay is one of several important steps in the photolithography area of semiconductor manufacturing. Overlay control involves measuring the misalignment between two successive patterned layers on the surface of a semiconductor device. Generally, alignment is important to ensure that the multiple layers of the semiconductor devices are connected and functional. As technology facilitates smaller critical dimensions for semiconductor devices, the need for reduced of misalignment errors increases dramatically.
Generally, photolithography engineers currently analyze the overlay errors a few times a month, many times, to observe trends in manufacturing processes. The results from the analysis of the overlay errors are used to make updates to exposure tool settings manually. Some of the problems associated with the current methods include the fact that the exposure tool settings are only updated a few times a month. Furthermore, currently the exposure tool updates are performed manually.
Generally, a set of processing steps is performed on a lot of wafers on a semiconductor manufacturing tool called an exposure tool or a stepper. The manufacturing tool communicates with a manufacturing framework or a network of processing modules. The manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which the stepper is connected, thereby facilitating communications between the stepper and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process. The input parameters that control the manufacturing process are revised periodically in a manual fashion. As the need for higher precision manufacturing processes increases, improved methods are needed to revise input parameters that control manufacturing processes in a more automated and timely manner. Furthermore, wafer-to-wafer manufacturing variations can cause non-uniform quality of semiconductor devices.
A known technique for evaluating the acceptability of the photolithography process involves measuring critical dimensions or other parameters after the photoresist has been developed. One method used to evaluate the developed wafer is to use scatterometry to generate an intensity measurement indicative of the pattern on the wafer. The pattern in the developed photoresist appears as a series of trenches. Light is reflected differently in the trenched vs. the non-trenched areas, resulting in a characteristic scattering pattern. The scatterometry measurements may be used to change the photoresist operating parameters, such as exposure time, post exposure bake time, develop time, etc. to affect the pattern formed on subsequent lots of wafers. The industry today lacks an efficient manner of utilizing scatterometry techniques to efficiently calculate overlay errors and reduce variabilites in processed semiconductor wafers.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided for overlay measurements using optical techniques. At least one semiconductor device is processed. Metrology data from the processed semiconductor device is acquired. A scatterometry overlay analysis based upon the metrology data is performed. At least one modified manufacturing parameter is calculated based upon the scatterometry overlay analysis.
In another aspect of the present invention, an apparatus is provided for overlay measurements using optical techniques. The apparatus of the present invention comprises: a computer system; a manufacturing model coupled with the computer system, the manufacturing model being capable of generating and modifying at least one control input parameter signal; a machine interface coupled with the manufacturing model, the machine interface being capable of receiving process recipes from the manufacturing model; a processing tool capable of processing semiconductor wafers and coupled with the machine interface, the first processing tool being capable of receiving at least one control input parameter signal from the machine interface; a metrology tool coupled with the first processing tool and the second processing tool, the metrology tool being capable of acquiring metrology data; a metrology data organizer coupled with the metrology, the metrology data organizer being capable of organizing the acquired metrology data; and a scatterometry data analysis unit coupled with the metrology data organizer and the computer system, wherein the scatterometry data analysis unit capable of performing a scatterometry overlay analysis to determine whether a significant overlay exists on a processed semiconductor wafer.